Dynamically Reconfigurable Analog Routing and Multiplexing Architecture on a System on a Chip

ABSTRACT

An integrated circuit device may include a reconfigurable analog signal switching fabric comprising a plurality of global buses that are selectively connected to external pins by pin connection circuits in response to changeable analog routing data, and a plurality of local buses that are selectively connected to analog blocks and/or global buses by routing connection circuits in response to the analog routing data; and at least one processor circuit that executes predetermined operations in response to instruction data.

This application is a continuation application of U.S. non-provisionalpatent application having Ser. No. 12/776,323, filed on May 7, 2010,which claims the benefit of U.S. provisional patent application havingSer. No. 61/176,905, filed on May 9, 2009, the contents of which areincorporated by reference herein.

TECHNICAL FIELD

The present disclosure relates to integrated circuit devices, and moreparticularly to reconfigurable integrated circuit devices having digitaland analog circuit blocks.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 shows an integrated circuit device according to an embodiment.

FIG. 2 shows an integrated circuit device according to anotherembodiment.

FIG. 3 is a representation of an integrated circuit device architectureaccording to an embodiment.

FIG. 4 is a representation of an integrated circuit device architectureaccording to another embodiment.

FIG. 5 shows input/output (I/O) connection circuits according to anembodiment.

FIG. 6 shows I/O connection circuits according to a further embodiment.FIG. 7 shows a general purpose I/O configuration circuit according toone embodiment.

FIG. 8 shows a programmable analog routing fabric according to anembodiment.

FIGS. 9A to 9H show various analog block connection arrangementsaccording to particular embodiments.

FIGS. 10A to 10D show various signal path connections that may becreated with an analog routing fabric according to various embodiments.

FIG. 11 is a schematic diagram showing global I/O connections to busesof an analog routing fabric according to one embodiment.

DETAILED DESCRIPTION

Various embodiments will now be described that show devices and methodsof an integrated circuit device having a reconfigurable analog routingfabric for connecting input/outputs (I/Os) to one or more analog circuitblocks with multiple buses and connection circuits.

In the following description, like items are referred to by the samereference characters, but with the first digit(s) corresponding to thecorresponding figure number. Referring now to FIG. 1, an integratedcircuit device according to a first embodiment is shown in a blockdiagram and designated by the general reference character 100. In someembodiments, a device 100 may be a “system-on-chip” that provides bothprogrammable analog functions as well as programmable digital functions.As shown in FIG. 1, a device 100 may include a number of externalconnection pins (one shown as 102), an analog section 104, and a digitalsection 106. Pins (e.g., 102) may provide a physical signal connectionto device 100, and may be input pins, output pins, or pins serving asboth an input and an output. Such pins (e.g., 102) will be referred toherein as input/output (I/O) pins, it being understood such pins serveas (or may be configured to serve as) an input, output or both. In someembodiments, pins (e.g., 102) may be configured as either analog pins(i.e., input or output analog signals) or digital pins (i.e., input oroutput binary logic signals). Further, in some embodiments, pins (e.g.,102) may be dedicated pins (e.g., only digital input and/or outputpins).

An analog section 104 may include a programmable analog routing fabric108 and a number of analog blocks 110-0 to -n.

Analog routing fabric 108 may be configured (and reconfigured) toprovide signal paths between I/O pins (e.g., 102) configured as analogI/Os and any of analog blocks (110-0 to -n). As but a few examples, ananalog routing fabric 108 may provide pin-to-pin paths via one orseveral buses, enable several pins to be connected to a single bus,enable several buses to be connected to a single pin, and/or enable anyanalog I/O pin to be connected to any analog block (110-0 to -n).

An analog routing fabric 108 may be programmed (and reprogrammed)according to analog routing data. As will be described below, incontrast to conventional approaches, such analog routing data may beprovided from any of a number of different sources, rather than onlyfrom an on-board processor. In a particular embodiment, an analogrouting fabric 108 may include multiple buses that may be connected toone another by connection circuits based on analog routing data.

Analog blocks (110-0 to -n) may include analog circuits that executeanalog circuit functions. Analog blocks (110-0 to -n) may be connectedto I/O pins (e.g., 102) and/or to one another by analog routing fabric108. Selected or all of analog blocks (110-0 to -n) may also receiveand/or output digital data to digital section 106. Analog blocks (110-0to -n) may include various analog circuits, including but not limited tocapacitance sense circuits, comparators, analog-to-digital-converters(ADCs) (including “sigma-delta” types and/or successive approximationtypes), filters (including low pass filters), switched capacitor typecircuits, and/or digital-to-analog converters (DACs) (including bothcurrent and/or voltage DACs).

It is understood that all or a portion of analog routing fabric 108 maybe configured dynamically (changed during the operation of a device 100)or statically (maintained substantially the same throughout theoperation of device 100).

In the embodiment shown, a digital section 106 may include a processorsection 112, a direct memory access (DMA) circuit 114, an analoginterface I/F circuit 116, a data transfer hub circuit 118, aprogrammable reference generator 120, programmable digital section 122,and a digital system interconnect (DSI) 124. A processor section 112 mayinclude one or more processors that may execute predeterminedinstructions. A processor section 112 may one source for providinganalog routing data for configuring analog routing fabric 108.

A DMA circuit 114 may enable transfers of data between device 100 andother devices without direct control of processor section 112. A DMA 114may also be a source of analog routing data for configuring analogrouting fabric 108. This is in sharp contrast to conventional approachesthat limit programmability of a routing fabric to data issued from aprocessor, or the like. While the embodiment of FIG. 1 shows a DMAcircuit 114, other embodiments may include different types of datatransfer circuits that may serve as a source of analog routing dataindependent of a processor section 112.

An analog I/F circuit 116 may receive analog signals, and convert themto a digital domain. An analog UF circuit 116 may be a further source ofanalog routing data for configuring analog routing fabric 108.

A data transfer hub circuit 118 may provide a data transfer path betweena processor section 112 and devices external to device 100, as well aslocations within device 100. As but a few of the many possible examples,a data transfer hub 118 may enable data transfers to one or moreinterfaces for communicating with external devices, including one ormore external memory interfaces, one or more serial data transferinterfaces, and/or one or more I/Os (e.g., 102). Data transfer hub 118may also transfer data between on board (i.e., circuits of the samedevice) sections, including internal memory circuits, interrupt controlcircuits, power management circuits, timing circuits, analog interfacecircuit 116, programmable digital section 122 and/or DSI 124.

A programmable reference generator 120 may generate reference currentsand/or voltages that may be used in analog section 104. Such programmedcurrents/voltages may also be provided as output values from device 100.A programmable digital section 120 may provide programmable logiccircuits that may be configured into various digital functions based ondigital configuration data. In very particular embodiments, aprogrammable digital section 120 may include programmable logic deviceblocks with programmable functions, and programmable interconnections.Programmable digital section 120 may be yet another source of analogrouting data for configuring analog routing fabric 108.

A DSI 124 may enable interconnections between various parts of thedigital section 106, and in addition may provide digital connections toanalog section 104. More particularly, DSI 124 may provide analogrouting data, or signals generated from such routing data, todynamically configure analog routing fabric 108. In very particularembodiments, a DSI 124 may enable analog routing fabric 108 to beconfigured from any of: processor section 112, direct access circuit114, analog I/F circuit 116 and/or programmable digital section 122.Though not shown in FIG. 1, a DSI 124 may also provide connections tofixed digital function blocks.

In this way, an integrated circuit may include analog circuit blocksconnected to I/O pins with an analog routing fabric reconfigurableaccording to analog routing data from various sources in addition to aprocessor.

Referring now to FIG. 2, an integrated circuit device according to afurther embodiment is shown in a block diagram and designated by thegeneral reference character 200. The device of FIG. 2 may be oneimplementation of that shown in FIG. 1.

In the embodiment of FIG. 2, pins may include general purpose I/O (GPIO)pins (one set shown as 202-0), special I/O pins (SIO) (one set shown as202-1), and direct connection pins (three sets shown as 202-2/3/4).

GPIO pins 202-0 may be connected to corresponding GPIO configurationcircuits (one shown as 226). GPIO configuration circuits (e.g., 226) mayenable a GPIO pin to be connected to an analog interconnect 230 and/or aDSI 224. Accordingly, when connected to analog interconnect 230, a GPIOpin (e.g., 202-0) may serve as an analog input and/or output.Conversely, when connected to DSI 224, a GPIO pin (e.g., 202-0) mayserve as a digital input and/or output. A GPIO configuration circuit(e.g., 226) may also provide different types of connections to analoginterconnect 230. In particular, a GPIO pin may be connected one or moredifferent buses of an analog interconnect 230.

SIO pins (e.g., 202-1) may be connected to SIO configuration circuits(e.g., 226). SIO configuration circuits (e.g., 228) may enable an SIOpin to be connected to DSI 224. Accordingly, SIO pins (e.g., 202-1) maybe programmable as a digital input and/or output. However, such pins(e.g., 202-1) may not serve as an analog I/O.

Direct connection pins (e.g., 202-2/3/4) may have a direct connection toparticular circuit sections of device 200. Set 202-2 may only provideconnections to one particular interface circuit. In contrast, set 202-3may provide a direct connection to a digital circuit, as well as a GPIOconfiguration circuit (e.g., 226), while set 202-4 may provide a directconnection to an analog circuit block, as well as a GPIO configurationcircuit (e.g., 226).

Referring still to FIG. 2, an analog block group 210 in combination withGPIO configuration circuits (e.g., 226) and analog interconnect 230 mayform an analog routing fabric. Analog block groups 210 may include anumber of analog blocks (ALOG BLK0 to n) which may be connected to GPIOsthrough analog interconnect 230 and GPIO configuration circuits (e.g.,226), and to one another through analog interconnect 230. Analog blocks(ALOG BLK0 to n) may take the form of those shown as 110-0 to -n, orequivalents.

Analog interconnect 230 may include a number of buses and connectioncircuits to enable reconfigurable interconnection between GPIOconfiguration circuits (e.g., 226) and analog block group 210. In aparticular embodiment, analog interconnect 230 may include: global busesthat may enable signal paths to be created between GPIOs and any or allof analog blocks (ALOG BLK0 to n), local buses that may enable signalpaths to be created between any or all of analog blocks (ALOG BLK0 ton), and multiplexer buses that may enable one bus to connect multipleGPIOs to any or all of analog blocks (ALOG BLK0 to n).

In FIG. 2, a digital section 206 may include a memory system 232, aprocessor system 234, a program and test system 236, and a digitalsystem 238.

A memory system 232 may include a memory I/F 242 and one or morememories (MEMO to i). A memory I/F 242 may enable external access tomemory devices by device 100. Memories (MEMO to -i) may include varioustypes of memories, including but not limited to a static random accessmemory (SRAM), nonvolatile memory (including EEPROMs, and flash EEPROM).Such memories (MEMO to -i) may be directly accessible by processorsystem 234.

A processor system 234 may include a processor 212 as well as peripheralaccess system 240. A processor 212 may include one or more processors aswell as corresponding circuits such as memory controller (includingcache controllers) and an interrupt control circuit. A peripheral accesssystem 240 may include circuits such as a direct access circuit, likethat shown as 114 in FIG. 1 and/or a data transfer hub circuit, likethat shown as 118, or equivalents.

A program and test system 236 may include circuits that enable data tobe loaded into memory system 232 (program data for execution byprocessor system 234), as well as test circuits for providing test datato and test result data from a device 200.

Memory system 232 and processor system 234 may be connected to a systembus 244. A system bus 244 may also be connected to analog block group210.

A digital system 238 may include programmable digital section 222 aswell as a number of fixed function digital blocks (FIXED BLK0 to -j).Programmable digital section 222 may be like that shown as 122 in FIG.1, or an equivalent. Fixed function digital blocks (FIXED BLK0 to -j)may provide predetermined digital functions for device. Fixed functiondigital blocks (FIXED BLK0 to -j) may include any suitable digitalcircuit, including but not limited to timer circuits, counter circuits,digital modulation circuits, serial interface circuits, and/or networkinterface circuits. In the particular embodiment shown, digital system238 may be connected to a fixed interface circuit 246, which may be aphysical layer (PHY) interface circuit.

A DSI 224 may provide digital connection between various sections of thedigital system 238 and/or connections to suitably configured GPIO pins(e.g., 202-0) or SIO pins (e.g., 202-1).

In the particular embodiment shown, a device may also include systemresources 248. System resources 248 may include a clock system 250 and apower management system 250. A clock system 250 may provide timingsignals to various portions or a device 200 based one or more clockgeneration circuits and/or one or more received timing signals. A powermanagement system 250 may provide power supply voltages and regulationto various portions of device 200. A power management 250 mayselectively disable portions of the device for low power (i.e., sleep)modes of operation.

In this way, an integrated circuit may include I/Os programmable toconnect to one or more buses of an analog interconnect to enableconnections between I/Os and/or to analog blocks.

Referring now to FIG. 3, an integrated circuit device configurationarchitecture according to an embodiment is shown in a block schematicdiagram and designated by the general reference character 300.

Architecture 300 shows programmable digital section 322, fixed functiondigital blocks 354-0/1, processor system 334 and peripheral accesssystem 340 connected to a DSI 324. A DSI 324 may provide digital signalpaths between various circuits connected to it. In one very particularembodiment, such a connection may be configurable through programmabledigital section 322.

DSI 324 may also be connected to analog route configuration circuit 356.Analog route configuration circuit 356 may provide configuration valuesto analog routing fabric 308 to enable reconfigurable connectionsbetween GPIOs 302-0 and analog blocks 310-0/1. In one embodiment, analogroute configuration circuit 356 may be accessible via any of the othercircuit blocks connected to DSI 324, enabling analog routingconfiguration via multiple sources. In a very particular embodiment,analog route configuration circuit 356 may include, or be the output of,configuration registers that may be written to contain analog routingdata. Such analog routing data may be updated to dynamically change ananalog routing configuration. In the particular embodiment of FIG. 3,analog routing fabric 308 is represented by various connection elements360 controlled by analog route configuration circuit 356. Connectionelements 360 may provide connections between buses (not shown), GPIOs302-0, and analog blocks 310-0/1. In particular embodiments, connectioncircuit elements 360 may be controlled in groups as connection circuits.Such connection circuits may have a switch configuration, allowing anynumber of connection elements of a group to be enabled in response toanalog routing data. Alternatively, connection circuits may have amultiplexer (MUX) configuration, allowing only one connection element tobe enabled in the group at one time. It is understood that FIG. 3 showsbut two analog blocks 310-0/1and two GPIOs 302-0 for illustrationpurposes. A device 300 may include additional blocks and connections asshown in the other embodiments described herein, and equivalents.

FIG. 3 also shows a GPIO a configuration circuit 326 and SIOconfiguration circuit 328. A GPIO configuration circuit 326 may providea digital input and/or output path to DSI 324, as well as one or moreconnections (only one shown) as part of the analog routing fabric 308.In contrast, SIO configuration circuit 328 may provide only a digitalconnection to DSI 324.

In this way, an integrated circuit device may include an analog routingfabric controlled by an analog route configuration circuit connected toany one of a number of digital blocks by a configurable digital systeminterconnect.

Referring now to FIG. 4, an integrated circuit device configurationarchitecture according to a further embodiment is shown in a blockschematic diagram and designated by the general reference character 400.FIG. 4 includes many of the same items as FIG. 3, thus a description ofsuch items will be omitted.

FIG. 4 differs from FIG. 3 in that switch voltage generator circuits460-0 to -i may be included the generate switch voltages Vsw0 to Vswithat may be outside of a power supply voltage received by an integratedcircuit 400. For example, a switch voltage (Vsw0 and/or Vswi) may behigher than a high power supply voltage or lower than a low power supplyvoltage. Switch voltage generator circuits (460-0 to -i) may receiveconfiguration values from DSI 324. Consequently, switch voltagegenerator circuits (460-0 to -i) may be configured (and reconfigured) insubstantially the same manner as analog routing fabric 308 (e.g.,multiple sources). In one particular embodiment, voltage generatorcircuits 460-0 to -i may be charge pump circuits.

In the embodiment shown, a switch voltage (Vsw0 and/or Vswi) may beapplied to connection elements 360 by switch activation circuits 458-0/1according to configuration values received from analog routeconfiguration circuit 356. In this way, an integrated circuit device mayinclude a programmable analog routing fabric having connection elementsoperated by voltages levels outside the range of received power supplyvoltages.

As noted above, in some embodiments, I/O pins may be selectivelyconnected to one or more buses of an analog routing fabric to enableanalog signal paths between such I/O pins and one or more analog blocks.Particular I/O connection circuits according to one embodiment will nowbe described with reference to FIG. 5.

Referring to FIG. 5, I/O connection circuits according to an embodimentare shown in a block schematic diagram and designated by the generalreference character 500. I/O connection circuits 500 may form part of aprogrammable analog routing fabric of embodiments shown herein.

I/O connection circuits 500 may include a number of I/O pins 502-0 to-k, I/O connection circuits 562-0 to -k, analog MUX buses (AMXBUS0/1)564-0/1, a number of global buses 566-0 to -h, an analog blockconnection circuit 568, an analog block 510, and an analog routingsignal source 572.

I/O connection circuits (562-0 to -k) may receive first analog routingdata 574-0 and second routing data 574-1, and in response, connect acorresponding I/O pin (502-0 to -k) to AMXBUS0 564-0 and/or acorresponding global bus (566-0 to-h). I/O connection circuits (562-0 to-k) may operate in a switch or MUX like fashion as noted above. It isunderstood that each I/O connection circuit (562-0 to -k) may connectits corresponding I/O pin (502-0 to -k) to other global buses not shown.

Referring still to FIG. 5, an analog block connection circuit 568 mayconnect any of AMXBUS0/1 564-0/1 to analog block 510 based on thirdanalog routing data 574-2.

A routing value source 572 may provide routing data to dynamicallyreconfigure connections between I/Os and buses. In the particularembodiment of FIG. 5, a routing value source 572 may include any of: aprogrammable digital section 522, a direct access circuit 514, or aprocessor section 512 that provide routing data by way of a DSI 524. Itis understood that routing data 574-0/1/2 may be dynamic, changing overtime according to operations of a device.

In this way, any of multiple I/O pins may be selectively connected toglobal buses and/or an analog MUX bus, where the analog MUX bus providesa path to one or more analog blocks.

Referring to FIG. 6, I/O connection circuits according to anotherembodiment are shown in a block schematic diagram and designated by thegeneral reference character 600. I/O connection circuits 600 may formpart of a programmable analog routing fabric of embodiments shownherein, and may be used in combination with those shown in FIG. 5. FIG.6 includes many of the same items as FIG. 5, thus a description of suchitems will be omitted.

FIG. 6 may differ from FIG. 5 in that a global bus connection circuit676 may connect any of global buses (566-0 to -h) to analog block 510based on fourth analog routing data 574-2.

In this way, I/O pins may be connected to global buses, any of which maybe selectively connected to one or more analog blocks.

As noted in embodiments above, a GPIO pin may serve as an analog I/O ora digital I/O. One very particular GPIO configuration circuit such afunction is shown in FIG. 7.

Referring to FIG. 7, a GPIO configuration circuit according to oneembodiment is shown in a block schematic diagram, and designated by thegeneral reference character 700. A GPIO configuration circuit 700 may beone example of that shown as 226 in FIG. 2.

A GPIO configuration circuit 700 may include a digital input path 778, adigital output path 780, an analog path 782, and an auxiliary functionpath 784. A digital path 778 may include an input driver 786 having aninput coupled to GPIO pin 702 and an output that provides a digitalsystem input signal. In one embodiment, such a digital input signal maybe provided to a DSI (not shown). Input driver 786 may be controlled bydigital control signals (DIG. CTRL). An output of input driver 786 mayalso be connected to interrupt logic 788 which may generate interrupts(INTRUPTs) for other circuits of the device.

A digital output path 780 may include an output driver 790 having aninput that receives a digital system output signal. Such a digitaloutput signal may be provided from a DSI. Output driver 790 may driveGPIO pin 702 in response to such a digital output signal. An outputdriver 790 may control a drive strength and/or slew of an output signalin response to digital output control signal (DIG_OUT_CTRL). In responseto a bi-directional control signal (BI-DIR CTRL), digital output path780 may be disabled (and digital input path 778 enabled).

An analog path 782 may include an I/O connection circuit 762 that mayselectively connect GPIO pin 702 to a global bus 766 and/or an analogMUX bus 764 in response to routing data 774 and output data from globalcontrol logic 792. Global and analog MUX buses may take the form of anyof those shown in other embodiments herein, and equivalents.

In the very particular embodiment shown, an auxiliary function path 784may drive a GPIO 702 with a generated bias voltage VBIAS based on adigital output signal. In a very particular embodiment, an auxiliaryfunction path 784 may be a liquid crystal display (LCD) bus, for drivingLCD elements. Having described various embodiments with programmableanalog routing fabrics, an analog routing fabric according to one veryparticular embodiment is shown in a block schematic diagram in FIG. 8,and designated by the general reference character 808.

FIG. 8 shows a routing fabric 808 that may connect GPIO pins (one shownas 802) to any of analog blocks (810-00 to 810-1 n) by way of analog MUX(AMUX) buses 864-0/1, global buses 866-0/1 and/or local buses 896-0/1.Routing fabric 808 may be conceptualized as having a left and rightside, with a left side including one left AMUX bus 864-0, eight leftglobal buses (0-7) 866-0, and four left local buses (896-0). A rightside may include one right AMUX bus 864-1, eight right global buses(0-7) 866-1, and four right local buses (896-1).

Programmable connections between the various buses, GPIO pins, andanalog blocks are shown by circles (one shown as 885). Each programmableconnection may be dynamically enabled or disabled in response to analogrouting data to configure a routing fabric for desired analog functions.In some embodiments, programmable connections may vary in impedance,with some having a lower on impedance than others. In particular,connections to impedance sensitive analog blocks may have a lowerimpedance value than other connections.

Connections surrounded by dashed lines may denote a connection group. Aconnection group may operate in a switch mode (any of the connectionscan be enabled) and/or MUX mode (only one connection enabled), as notedabove. Connection groups may take various forms including but notlimited to: I/O connection groups (one shown as 894) that may connect acorresponding GPIO pin to global buses and/or an AMUX bus; referenceconnection groups (one shown as 898), that may connect referencevoltages and currents to one or more buses or analog blocks, powersupply connection groups (one shown as 891) that may connect powersupply voltages to one or more buses; block connection groups (one shownas 887) that may connect an analog block to any of multiple buses. It isnoted that the embodiment of FIG. 8 shows connection blocks withconnections to substantially all available buses. As will be shownbelow, in particular embodiments, connection may be provided to onlyselected buses.

Programmable connections may also include any of: individual referenceconnections (one shown as 897) that may provide a single referencevoltage (or current) to a bus or analog block; AMUX joining connections(one shown as 895) that may connect one AMUX bus to another; globaljoining connections (one shown as 893) that may connect a left hand sideglobal bus to a corresponding right hand side global bus; and localjoining connections (one shown as 889) that may a left hand side localbus to a corresponding right hand side local bus.

Referring still to FIG. 8, AMUX buses 864-0/1 may enable any of GPIOpins (e.g., 802) to be connected to any of analog blocks (810-00 to -1n). Global buses 866-0/1 may connect selected GPIOs to analog blocks(810-00 to -1 n). Local buses 896-0/1 may enable analog blocks (810-00to -1 n) to be connected to one another.

In some embodiments, selected or all buses 864-0/1, 866-0/1, 896-0/1 maybe shielded, to limit signal coupling between buses (and other signallines). Shielding may include forming a shielding conductor adjacent tosuch bus lines, a maintaining the shielding conductor at a potentialthat limits signal coupling, or any other suitable shielding techniques.In a very particular embodiment, local buses 896-0/1 and global buses866-0/1 may be shielded.

In this way, an analog routing fabric may include: analog MUX buses thatmay dynamically connect multiple GPIOs to one or more analog blocks,unified global buses that may connect selected GPIOs to analog blocks,and local buses that may connect analog blocks to one another.

Having described embodiments with analog blocks connected to buses of aswitching fabric, very particular examples of analog block connectionswill now be described.

Referring to FIG. 9A, an example of an analog block connection is shownin a block schematic diagram and designated by the general referencecharacter 985-A. An analog block 910-A may be a filter block having twofilters, one filter may have an input (in0) connectable to a left AMUXbus 964-0 and/or left global bus 0 by a connection group 987-A. Acorresponding output (out0) may be connected to a local bus 0. A secondfilter may have similar connections to corresponding right hand sidebuses.

Referring to FIG. 9B, another example of an analog block connection isshown in a block schematic diagram and designated by the generalreference character 985-B. An analog block 910-B may be a comparatorblock having four comparators, each having a “+” input and a “−” input.Such inputs may be connected to selected buses and/or reference voltagesby connection groups (one shown as 987-B). In the embodiment shown,comparator block 910-B may provide comparator results (cmp_results) asdigital data. In a particular embodiment, a digital data may be providedto a DSI (not shown). Referring to FIG. 9C, another example of an analogblock connection is shown in a block schematic diagram and designated bythe general reference character 985-C. An analog block 910-C may be acapacitance sense block having two sense circuits, each having an output(out), an reference input (ref), and a signal input (in). In theembodiment shown, outputs (out) may have a “hard” (i.e.,nonprogrammable) connection 985 to AMUX buses 964-0/1. In addition,another analog block (in this example a DAC block 910-x), mayselectively provide a reference value to a reference input throughconnection group 987-C.

FIG. 9D shows an analog block connection for a switchedcapacitor/continuous time analog circuit block 985-D. Connections areunderstood from the above descriptions.

FIG. 9E shows an analog block connection for a voltage or current DAC(VIDAC) block 985-E. VIDAC block 985-E shows an arrangement in whichoutputs (v0, v1) from the analog block 910-E may be provided as inputsto other analog blocks (910-z0/1). A VIDAC block 985-E may receive inputdigital values (DIG_IN) for conversion. In particular embodiments, suchdigital values may be received from a DSI. FIG. 9E also shows anarrangement in which GPIOs (one shown as 902) may be connected to ananalog block 910-E by an I/O connection 981, rather than by buses.Further in the embodiment shown, VIDAC 985-E may only have connectionsto left side buses.

FIG. 9F shows an analog block connection for a delta-signal modulationADC (DSM) block 985-F. Connections are understood from the abovedescriptions. A DSM block 985-F may output digital data (VALUE)reflecting conversion results. In a particular embodiment, a digitalconversion results may be provided to a DSI (not shown).

FIG. 9G shows an analog block connection for an operational amplifier(op amp) block 985-G. Connections are understood from the abovedescriptions. FIG. 9G shows an arrangement in which analog block 985-Gmay have inputs (+,−) connected to lines of local buses 964-0, lines ofglobal buses 966-0, or a reference value (V0). However, in addition,such inputs may also be connected to GPIO pins (one shown as 902-0G) by

I/O connection (one shown as 981). Further, a negative feedback pathbetween an (−) input and an output of each op amp may be enabled by acircuit connection (one shown as 979). Still further, op amp outputs mayalso have a direct connection to certain GPIO pins (one shown as902-1G).

FIG. 9H shows an analog block connection for a successive approximation(SAR) ADC block 985-H. Connections and digital output values areunderstood from the above descriptions.

Having described programmable analog routing fabrics and analog blockconnections to such fabrics, methods of providing connection pathsaccording to very particular embodiments will now be described. In thebelow figures, solid circles designate enabled connections to buses.

Referring to FIG. 10A, two of numerous signal routes that may be formedin analog routing fabric 808 of FIG. 8 are shown by bold lines. Route1077-0 shows how different GPIO pins 1002-2 and 1002-3 may be connectedto one another by a single bus, which in the example shown is left AMUXbus 864-0. Route 1077-1 shows how different GPIO pins 1002-0 and 1002-1may be connected to one another by a multiple different buses, which inthe example shown, includes right global bus “7”, left global bus “7”,and left global bus “3”.

Referring to FIG. 10B, more signal routes that may be formed in analogrouting fabric 808 of FIG. 8 are shown by bold lines. Routes 1077-2 to-4 shows how different GPIO pins 1002-4, -5, -6 may be connected to asame bus, which in the example is right global bus “7”. FIG. 10B alsoshows how a single GPIO pin 1002-7 may be connected to multiple buses,which in this example are left global buses 4-7.

Referring to FIG. 10C, additional examples of possible signal routes inan analog routing fabric 808′ like that of FIG. 8 are shown by boldlines. FIG. 10C shows how GPIO pins 1002-8 to -10 may all be connectedto a same analog block 810-00 at different signal points. In particular,GPIO pin 1002-8 may be connected by right and left AMUX buses 864-0/1,GPIO pin 1002-10 may be connected by left global bus “0”, and GPIO pin1002-9 may be connected by right global bus “6” and left global bus “6”.

FIG. 10C also shows how local buses may be utilized to connect analogblocks together. In the particular embodiment shown, analog blocks810-1n and 810-10 may be connected together by right local bus “2”, andanalog block 810-10 and 810-0 n may be connected together by left localbus “3” and right local bus “3”.

Referring now to FIG. 10D, still further examples of possible signalroutes in an analog routing fabric 808 like that of FIG. 8 are shown bybold lines. FIG. 10D shows how multiple GPIO pins 1002-11 to -14 mayeach be connected to different analog blocks. In particular, GPIO pins1002-11 to -14 may be connected to analog blocks 810-00, -0 n, -10 and-1 n, respectively.

FIG. 10D also shows how multiple GPIO pins 1002-15 to -17 may each beconnected to a same analog block input or output. In particular, GPIOpins 1002-15 to -17 may all be connected to a same I/O of analog blocks810-00.

As noted above, according to some embodiments, GPIO pins may haveparticular connections to buses. GPIO bus connections according to oneparticular embodiment are shown in FIG. 11.

Referring to FIG. 11, a portion of an analog routing fabric like that ofFIG. 8 is shown in schematic diagram and designated by the referencecharacter 808″. FIG. 11 shows various GPIO pins 1102-0 to -11 andpossible connections to buses. In particular, FIG. 11 shows how all GPIOpins 1102-0 to -11 may have a connection to a same analog MUX bus 864-1,and have connections to only selected global buses.

It should be appreciated that in the foregoing description of exemplaryembodiments. Various features are sometimes grouped together in a singleembodiment, figure, or description thereof for the purpose ofstreamlining the disclosure aiding in the understanding of one or moreof the various inventive aspects. This method of disclosure, however, isnot to be interpreted as reflecting an intention that the inventionrequires more features than are expressly recited in each claim. Rather,as the following claims reflect, inventive aspects lie in less than allfeatures of a single foregoing disclosed embodiment. Thus, the claimsfollowing the detailed description are hereby expressly incorporatedinto this detailed description, with each claim standing on its own as aseparate embodiment.

It is also understood that the embodiments of the invention may bepracticed in the absence of an element and/or step not specificallydisclosed. That is, a feature of the invention may be elimination of anelement.

Accordingly, while the various aspects of the particular embodiments setforth herein have been described in detail, the present invention couldbe subject to various changes, substitutions, and alterations withoutdeparting from the spirit and scope of the invention.

1.-20. (canceled)
 21. A method comprising: receiving first analogrouting data from at least one processor circuit; receiving secondanalog routing data from a programmable logic section comprising aplurality of digital programmable blocks formed in an integratedcircuit; configuring a dynamically or statically reconfigurable analogrouting fabric on the integrated circuit according to the first analogrouting data and the second analog routing data to selectively enableconnections and disconnections between one or more of a plurality ofanalog circuit blocks and a plurality of input/output (I/O) pins througha plurality of I/O connection circuits corresponding to the plurality ofI/O pins; and configuring the dynamically or statically reconfigurableanalog routing fabric to selectively connect a first analog circuitblock of the plurality of analog circuit blocks with a second analogcircuit block of the plurality of analog circuit blocks to provide ananalog function.
 22. The method of claim 21, further comprising:configuring the dynamically or statically reconfigurable analog routingfabric to selectively interconnect one or more of the plurality ofanalog circuit blocks with input/output (I/O) pins in response to analogrouting data from a direct memory access (DMA) circuit configured totransfer data between the integrated circuit and a source external tothe integrated circuit.
 23. The method of claim 21, wherein theplurality of I/O connection circuits comprise at least one of switchcircuits configured to provide connections between single fabric pointsand any of multiple other fabric points and multiplexer circuitsconfigured to provide a single connection between a single fabric pointand one of multiple other fabric points.
 24. The method of claim 21,further comprising: configuring one of the plurality of I/O connectioncircuits of the dynamically or statically reconfigurable analog routingfabric to selectively connect an I/O pin corresponding to an I/Oconnection circuit to at least one of a multiplexer (MUX) bus and atleast one of a plurality of global buses, wherein the global buses areconnectable to the analog circuit blocks through the dynamically orstatically reconfigurable analog routing fabric.
 25. The method of claim21, further comprising: configuring one of the plurality of I/Oconnection circuits of the dynamically or statically reconfigurableanalog routing fabric to selectively connect a corresponding analogcircuit block to any of a plurality of local buses, wherein the localbuses are connectable to the I/O pins through the dynamically orstatically reconfigurable analog routing fabric.
 26. The method of claim21, wherein the plurality of analog circuit blocks comprises at leasttwo of an analog signal filter, a comparator, a capacitance sensingcircuit, a switched capacitor circuit, a digital-to-analog converter, ananalog-to-digital converter, an operational amplifier, or a programmablevoltage reference.
 27. A system comprising: a plurality of externalconnection pins; a digital section coupled to a first subset of theplurality of external connection pins, the digital section comprising aprocessor circuit, a memory circuit and a plurality of digitalprogrammable blocks; and an analog section coupled to a second subset ofthe plurality of external connection pins, the analog section comprisinga plurality of analog circuit blocks and a dynamically or staticallyreconfigurable analog routing fabric configured to selectively connectand disconnect one or more of the plurality of analog circuit blocks thesecond subset of the plurality of external connection pins through aplurality of input/output (I/O) connection circuits in response to firstanalog routing data received from the processor circuit and secondanalog routing data received from the plurality of digital programmableblocks, and to selectively connect a first analog circuit block of theplurality of analog circuit blocks with a second analog circuit block ofthe plurality of analog circuit blocks to provide an analog function.28. The system of claim 27, wherein the dynamically or staticallyreconfigurable analog routing fabric is configured to selectivelyinterconnect one or more of the plurality of analog circuit blocks withthe second subset of the external connection pins in response to analogrouting data from a direct memory access (DMA) circuit configured totransfer data between the system and a source external to the system.29. The system of claim 27, wherein the plurality of I/O connectioncircuits comprise at least one of switch circuits configured to provideconnections between single fabric points and any of multiple otherfabric points and multiplexer circuits configured to provide a singleconnection between a single fabric point and one of multiple otherfabric points.
 30. The system of claim 29, further comprising at leastone voltage generation circuit configured to: generate at least oneswitch voltage outside a range of power supply voltages received by thesystem; and provide the at least one switch voltage to at least one I/Oconnection circuit.
 31. The system of claim 27, wherein the plurality ofI/O connection circuits of the dynamically or statically reconfigurableanalog routing fabric are configured to selectively connect an externalconnection pin corresponding to an I/O connection circuit to at leastone of a multiplexer (MUX) bus and at least one of a plurality of globalbuses, wherein the global buses are connectable to the analog circuitblocks through the dynamically or statically reconfigurable analogrouting fabric.
 32. The system of claim 27, the plurality of I/Oconnection circuits of the dynamically or statically reconfigurableanalog routing fabric are configured to selectively connect acorresponding analog circuit block to any of a plurality of local buses,wherein the local buses are connectable to the external connection pinsthrough the dynamically or statically reconfigurable analog routingfabric.
 33. The system of claim 27, wherein the plurality of analogcircuit blocks comprises at least two of an analog signal filter, acomparator, a capacitance sensing circuit, a switched capacitor circuit,a digital-to-analog converter, an analog-to-digital converter, anoperational amplifier, or a programmable voltage reference.
 34. Aintegrated circuit comprising: a plurality of input/outputs (I/Os); adigital section selectively coupled to a first subset of the pluralityof I/Os, the digital section comprising a processor circuit, a memorycircuit and a plurality of digital programmable blocks; and an analogsection selectively coupled to a second subset of the plurality of I/Os,the analog section comprising a plurality of analog circuit blocks and adynamically or statically reconfigurable analog routing fabricconfigured to selectively connect and disconnect one or more of theplurality of analog circuit blocks to the second subset of the pluralityof I/Os in response to first analog routing data received from theprocessor circuit and second analog routing data received from theplurality of digital programmable blocks, and to selectively connect afirst analog circuit block of the plurality of analog circuit blockswith a second analog circuit block of the plurality of analog circuitblocks to provide an analog function.
 35. The integrated circuit ofclaim 34, wherein the dynamically or statically reconfigurable analogrouting fabric is configured to selectively interconnect one or more ofthe plurality of analog circuit blocks with the second subset of theplurality of I/Os in response to analog routing data from a directmemory access (DMA) circuit configured to transfer data between theintegrated circuit and a source external to the integrated circuit. 36.The integrated circuit of claim 34, wherein the plurality of I/Oscomprise at least one switch circuit configured to provide connectionsbetween single fabric points and any of multiple other fabric points andmultiplexer circuits configured to provide a single connection between asingle fabric point and one of multiple other fabric points.
 37. Theintegrated circuit of claim 36, further comprising at least one voltagegeneration circuit configured to: generate at least one switch voltageoutside a range of power supply voltages received by the system; andprovide the at least one switch voltage to at least one I/O.
 38. Theintegrated circuit of claim 34, wherein the second subset of theplurality of I/Os are configured to selectively connect an externalconnection pin corresponding to an I/O to at least one of a multiplexer(MUX) bus and at least one of a plurality of global buses, wherein theglobal buses are connectable to the analog circuit blocks through thedynamically or statically reconfigurable analog routing fabric.
 39. Theintegrated circuit of claim 34, wherein the second subset of theplurality of I/Os are configured to selectively connect a correspondinganalog circuit block to any of a plurality of local buses, wherein thelocal buses are connectable to the external connection pins through thedynamically or statically reconfigurable analog routing fabric.
 40. Theintegrated circuit of claim 34, wherein the plurality of analog circuitblocks comprises at least two of an analog signal filter, a comparator,a capacitance sensing circuit, a switched capacitor circuit, adigital-to-analog converter, an analog-to-digital converter, anoperational amplifier, or a programmable voltage reference.